In digital communications systems it is often advantageous to embed a client signal for transport in a series of ‘wrappers’ or frames of fixed length and repetition rate. Two such sequential frames 100 and 110 are shown in FIG. 1. Within each wrapper or frame 100 and 110, there are fixed locations 102 that carry the client data. There may additionally be locations that carry different and/or unrelated client signals, as well as overhead locations that support transport of the client signal and other functions.
Often, it is advantageous for the wrapper, e.g., frame 100 to have a frequency that is not locked (is asynchronous or plesiochronous) to the embedded client signal. Furthermore, it is sometimes required to maintain, at the client egress, substantially the same bit rate that the client had upon ingress. Such a relationship may be required, for example, when “full transparency” is required for the client transport, meaning that the exact bit sequence is replicated from ingress to egress. To meet these joint requirements, “asynchronous mapping” may be used to encapsulate the client signal in the wrapper. For example, as shown in FIG. 1, there are, in addition to the fixed client data locations 102, variable stuff locations 104 and 106 in frames 100 and 110 that contain, or do not contain, client data. By variably ‘stuffing’ (inserting null data) in variable stuff location, such as location 104, or inserting actual client data, e.g., in location 106, the client signal may be transported in a bit-for-bit transparent manner, and the ingress and egress client frequencies are the same, when measured over an extended period of time. The variable stuff locations 104 and 106 are often called “justification opportunities”. In frame 100, the justification opportunity may be signaled from the transmitter to the receiver whether or not each justification opportunity carries data or stuffing; the signaling channel reserved for this purpose is often called “justification control”.
FIG. 2 shows a transmitter including typical asynchronous mapping circuit 200. Mapping circuit 200 includes a clock and data recovery (CDR) circuit 202 that receives client data carried by an incoming client signal. The client data, which is received in serial form, is converted into a parallel stream of successive parallel n-bit words by serial to parallel converter circuit 203. The words are fed to a first-in-first-out (FIFO) memory or buffer 206. Such serial-to-parallel conversion is done to limit the rate at which data can be toggled, so that the data processing can be performed with a relatively low cost, high-density logic device, such as a complementary metal-oxide-semiconductor (CMOS) device. CDR circuit 202 also generates a clock signal that is fed to a divide-by-n circuit 204 (n being the parallel word width), which, in turn, supplies a further clock signal having an appropriate frequency to control the storage of data into FIFO buffer 206.
The contents of FIFO buffer 206 are supplied to a multiplexer 212 which combines justification control bits and the contents of FIFO buffer 206 into additional n-bit wide parallel words. Multiplexer 212 operates under control of a wrapper frame assembly state machine 210 that receives a clock signal from a free running transmitter clock 208 and is thus synchronous with this clock. Clock 208 also supplies a clock signal to FIFO 206 to control the output of data to multiplexer 212. The data output from FIFO 206 is selected by state machine 210 for each n-bit word in an output frame. For fixed client data locations, the data is derived from the output of FIFO 206. For justification opportunities, the wrapper or frame data is derived from either the data stored in FIFO 206 or a stuff value, depending upon the FIFO status. Namely, if the data fill level of FIFO 206 is above a threshold (as indicated, for example, by a half-fill indicator), state machine 206 may place data in the justification opportunity. If the fill level of FIFO 206 is below the threshold, state machine 210 may stuff the justification opportunity with null data. Justification control is also inserted in the frame in order to inform the receiver whether each justification opportunity contains client data or null bits or data, for example.
As further shown in FIG. 2, multiplexer 212 may also receive other inputs, in addition to the data from FIFO 206 and the justification control information, for example, overhead and additional client data channels. The n-bit wide parallel words output from multiplexer 212 are next fed to a parallel-to-serial converter 214, which, in turn, supplies a serial data stream that is provided to a transmitter (not shown) that may include a laser. That transmitter outputs a serialized optical output that includes the frames noted above. Preferably, the parallel data width n is chosen such that the wrapper frame construction is feasible, efficient and cost-effective given the appropriate logic technology (e.g., CMOS) included in the electronics of the transmitter.
FIG. 3 shows receiver circuitry 300 that decapsulates incoming frames and extracts the client data included therein. The frames are supplied to a clock and data recover circuit 302, which outputs data to a serial-to-parallel conversion circuit 303 and a clock signal to a divide-by-n circuit 304. Such serial-to-parallel conversion generates parallel n-bit wide words and is done to improve efficiency and/or to make the circuit realizable in a technology that is available and cost effective. The parallel words generated in receiver circuitry 300, however, may not necessarily have the same width as the parallel words generated in mapping circuit 200. Data is fed to a first-in-first-out (FIFO) memory or buffer 306, and divide-by-n circuit 304 supplies a clock with an appropriate frequency to a wrapper frame disassembly state machine 310 and client clock synthesis circuit 318. State machine 310 distinguishes client data (including justification opportunities) within the wrapper frame, such that only the client data is stored in FIFO buffer 306. Separately, clock synthesis circuit 318 synthesizes the clock or frequency of the client signal received by mapping circuit 200 by processing the received wrapper clock or frequency, fixed client data locations, and the justification control channel.
In particular, the client frequency is synthesized by processing the client phase information that is implicit in the received wrapper. An n-bit unit of client data that is received in a fixed client data location represents a phase advance of n wrapper bit-times. A n-bit unit of client data that is received in a justification opportunity (e.g., location 106 in FIG. 1) similarly represents a phase advance of n wrapper bit times. A stuffed justification opportunity (e.g., location 104 in FIG. 1) represents a phase advance of 0 bit times. It can be seen that the joint transmitter and receiver mechanisms described above operate such that no phase information is lost over an extended period of time; the net phase advance or phase determined by the receiver's client clock synthesizer exactly matches the client data received by the transmitter:
            ϕ      client        ⁡          (      t      )        =            ∑              τ        =        0            t        ⁢                  ⁢                  [                  (                                    D              F                        +                          D              J                                )                ]            *      n      *              B        w            φclient(t)=net client phase advanceDF=fixed data units receivedDJ=data units received in justification opportunitiesn=the size in bits of each word in the frameBW=wrapper bit time
The communicated client signal frequency can be determined from the above equation by taking the time derivative of each side of the equation.
In the bit-for-bit transmission of client signals or data, it is often advantageous or even required to minimize the generation of jitter and wander via the overall transmission processes. Jitter and wander generation represent a deviation in time from the temporal position of each transmitted bit or symbol at which it was received at the client ingress to mapping circuit 200 (neglecting a fixed transport delay). Frequency components of this deviation above 10 Hz are termed “jitter” and components below 10 Hz are termed “wander”. For example, minimal jitter and wander generation may be required for the transmission of SONET/SDH client signals.
FIG. 4a is an example of a timing diagram that shows phase or phase advance (401) and cumulative or accumulated phase advance (curve 402) relative to the transmission of frames 100 and 110. In the transmission/receive process described above, the communication of phase information (i.e., the cumulative phase advance 402) is distributed in fixed units of n wrapper bit times. In the example shown in FIG. 4a, this quantization of the phase advance information represents an error φe(t) in the phase (404).
Since the phase error 404 represents a deviation from the ideal phase (curve 406), the phase error can be treated as jitter and wander. In general, the generated jitter and wander can be removed from the signal by filtering in a phase-lock loop (PLL) that is part of the client clock synthesis circuit 318. However, there are two limitations in this regard. First, the low-pass cutoff frequency fc of the PLL is subject to practical limitations. Second, in some cases it is required to reproduce some components of the client signal wander that may have existed at the client ingress to mapping circuit 200 (normally, those components below a specified frequency fR). The receiver circuit 300 may have no information by which it can discriminate which wander components existed in the original client signal client input to mapping circuit 200 and which were induced by the transmission process. Therefore, filtering of the generated wander may preclude preservation of the characteristics of the original signal.